A highly desirable method for the debugging of any microprocessor based computer system is to access the system through the processor socket. With this technique, which is known as in-circuit emulation ("ICE"), the processor of the unit under test (the target) is removed and a second microprocessor (the host) is linked to the target through the processor socket of the target and performs an in-circuit emulation of the target processor. ICE technology, in general, has historically been plagued by three serious limitations.
The first limitation is that of having to control all ICE functionality externally from the target microprocessor chip. Target processor information must be routed off the microprocessor chip in order for the ICE control circuitry to have access to the data necessary to perform its functions. Information must then be routed back into the chip to control its operation. The amount of logic necessary to control the target processor chip and perform all required ICE functionality is substantial. The ICE circuitry cannot be physically located at the plug (i.e, the plug which contains the host/emulation processor and which is used in place of the target processor to debug the system). This necessitates the use of cables from the plug to the ICE control circuitry and buffers to drive these cables. This introduces delay and possibly loss of real time functionality.
The second limitation is cost. The costs associated with the use of ancillary logic, cables, and buffers manifests itself in higher product cost.
The third limitation is the manner in which trace/break operations must be performed. When the ICE control circuitry is required to initiate these operations, it must load a specialized control memory with code, which when executed by the target processor will put the processor in a desired state. The ICE control circuitry must then switch the source of the program code from normal program memory to this specialized control memory. While the processor is executing code from the specialized control memory, the ICE control circuitry must "stuff" whatever code is appropriate into the normal program memory. Program code source must then be switched back to the normal program memory. As a result of this peripheral activity which must take place, context switching cannot be performed in real time.
The present invention solves these limitations by utilizing a very large scale integrated in-circuit emulator ("VLSICE") concept. By incorporating all relevant ICE control circuitry on the processor chip, most of the foregoing limitations are eliminated. There is no longer any need to route target processor information off the chip for the ICE circuit to perform its trace/break and context switching functions. The extra cables and buffers are therefore no longer necessary. Real time trace/break operation can be achieved because the chip's state can be controlled internally without the need for a specialized control memory.
ICE technology has been hampered by four other more specific limitations. The first of these is the limited access which the ICE circuitry has to the processor's internal data during emulation mode. Typically, only the memory address lines (i.e., external memory when program memory shares the same space as data memory or program memory and external data memory if separate memories are used) are available to the environment outside of the chip. In order to cause a trace or break to occur, a programmer could use only a program memory address, opcode value, external data memory address, and/or external memory data value. This problem is further impacted by the inability of ICE circuitry to access internal data for a trace. Only the above-mentioned information plus the input/output ports are available as trace data.
The second limitation is the number of trigger conditions which can be used to cause a trace or break. Typically, ICE units utilize two registers each for trace and break trigger conditions. This restriction is necessitated by the limited board space available for ICE circuitry. Conditional arming and disarming of the specified trigger conditions does not currently exist. Thus, only relatively simple experiments can be performed.
The third limitation is the speed at which the ICE circuitry must operate. ICE circuitry must be capable of tracking a target processor's speed as it goes through a series of shrink processes. With each shrink, system clocking gets faster. Unless the ICE circuitry is designed with a sufficient speed margin, it will not be capable of keeping up with a shrunken chip operating at full speed.
The fourth limitation is the limited ability to debug multiprocessor configurations with multiple ICEs. In particular, processors which are targeted for distributed control applications necessitate the need for high functionality multi-ICE capability.
The present invention, as described below, eliminates these limitations by utilizing the VLSICE concept.